1. Technical Field
The present invention relates to a DLL (Delay Locked Loop) circuit and a method of controlling the same, and in particular, to a DLL circuit that outputs a clock having an improved duty ratio quality and a method of controlling the same.
2. Related Art
Generally, a DLL circuit is used to supply an internal clock having an earlier phase than a reference clock, which is obtained by converting an external clock, for a predetermined time. The internal clock is generated to allow a semiconductor memory apparatus having relatively high integration, such as a synchronous DRAM (SDRAM) or the like, to operate in synchronization with the external clock.
More specifically, a clock input buffer receives the external clock and outputs the internal clock. At this time, the internal clock has a phase delayed from the phase of the external clock for a predetermined time by the clock input buffer. The phase of the internal clock is additionally delayed by delay elements in the semiconductor integrated circuit, and then transmitted to a data output buffer. Subsequently, the internal clock controls the data output buffer to output data.
Accordingly, there is a problem in that the output data is delayed as compared with the external clock. That is, a phase of the external clock is staggered with one of the output data.
To solve this problem, a DLL circuit is used. The DLL circuit adjusts the phase of the internal clock to be earlier than the external clock for a predetermined time. Accordingly, the output data is not delayed as compared with the external clock. That is, the DLL circuit receives the external clock and generates the internal clock having an earlier phase than the external clock for a predetermined time.
In a semiconductor memory apparatus, such as a DDR (Double Data Rate) SDRAM, which outputs data at rising time and falling time of the external clock, a dual loop type DLL circuit is used to generate a rising clock and a falling clock. The dual loop type DLL circuit includes feedback lines, each having a delay line, a delay modeling unit and a phase comparator. The individual delay lines perform coarse delay and fine delay operations according to an instruction from an operation mode setting unit to generate the rising clock and the falling clock. Further, in the DLL circuit, each feedback loop includes a phase mixer to perform an operation to adjust the duty ratio of the clock output from each of the delay lines to 50:50.
In the DLL circuit according to the related art, which includes a dual loop and controls the duty ratio of the clock using the phase mixer, after a delay locking operation of the clock is completed, only one feedback loop is activated, and the other feedback loop operates by being linked with the activated feedback loop. Accordingly, after the delay locking operation is completed, only one phase mixer is activated, and thus a clock generated does not have a correct duty ratio.
The phase mixer has a plurality of drivers that are provided at its pull-up section, a plurality of drivers that are provided at its pull-down section, and a driver that is provided to drive a voltage formed at a node between the pull-up section and the pull-down section. As such, the plurality of drivers provided in the phase mixer is controlled by a fixed control signal after the delay locking operation of the DLL circuit is completed. In this case, a change in driving ability between the pull-up section and the pull-down section may occur due to a change in PVT (Process, Voltage, and Temperature). However, the change cannot be adjusted by the fixed control signal. If the level of the voltage formed at the node between the pull-up section and the pull-down section is gradually changed due to the change in PVT, the duty ratio of an output clock may be significantly changed whenever each clock is input.
The DLL circuit according to the related art includes two feedback loops, each having a phase mixer, a delay modeling unit, a phase comparator, a duty ratio control unit, and the like. Accordingly, the area where the components are disposed is large. Further, power consumption of the individual components of the DLL circuit is high. As a result, low power consumption and high integration of the semiconductor integrated circuit are not easily realized.